Integrated circuit (ICs) manufacturers produce die on typically circular substrates referred to as wafers. A wafer may contain hundreds of individual rectangular or square die. Die on wafer, or unsingulated die, must be tested to determine good from bad before the dies are singulated. Unsingulated die testing traditionally occurs by physically probing each die at the die pads, which allows a tester connected to the probe to determine good or bad die. This type of probing is relatively slow and requires expensive mechanical mechanisms to accurately step and position the probe at each die location on the wafer. The probing step can damage the die pads which may interfere with the bonding process during IC packaging or assembly of bare die on MCM substrates. Also, as die sizes shrink, pads are positioned closer and closer together and it becomes more difficult and costly to design precision probing instruments to access them.
Alternate conventional methods for testing unsingulated die on wafers include: (1) designing each die to test itself using built-in-self-test (BIST) circuitry on each die and providing a way to enable each die BIST circuitry to test the die, (2) widening the scribe lanes between the die to allow for: (a) test probe points, (b) test access conductors, and/or (c) test circuitry, and (3) processing an overlying layer of semiconductor material with test circuitry over the die on wafers and providing via connections, from the overlying layer, to the pads of each die on the wafer. Method 1 disadvantageously requires BIST circuitry on the die which takes up area, and the BIST circuitry may not be able to adequately test the I/O of the die. Method 2 disadvantageously reduces the number of die that can be produced on a wafer since the widening of the scribe lanes takes up wafer area which could be used for additional die. Method 3 disadvantageously requires additional wafer processing steps to form the overlying test connectivity layer on top of the die on wafers, and also the overlying layer needs to be removed from the wafer after testing is complete. This overlying layer removal step is additive in the process and the underlying die could be damaged during the removal step.
Ideally, only good die are singulated and packaged into ICs. The cost of packaging die is expensive and therefore the packaging of bad die into ICs increases the manufacturing cost of the IC vendor and results in a higher cost to the consumer.
FIG. 1 illustrates a schematic of a die containing functional core logic (FCL) and input and output buffering to pad locations. The variety of pad buffering shown includes: inputs (I), 2-state outputs (2SO), 3-state outputs (3SO), open drain outputs (ODO), input and 3SO bidirectionals (I/O1), and input and ODO bidirectionals (I/O2). The FCL could be a custom or semicustom (ASIC) implementation comprising: microprocessors, combinational logic, sequential logic, analog, mixed signal, programmable logic, RAMs, ROMs, Caches, Arrays, DSPs, or combinations of these and/or other functions. The die is shown having a top side A, right side B, bottom side C, and left side D for convenience of description in regard to its position on the wafer. The die also has at least one voltage supply (V) pad and at least one ground (G) pad for supplying power to the die. Side A has pad locations 1-7, B has pad locations 1-8, C has pad locations 1-8, and D has pad locations 1-9. The arrangement of the buffer/pad combinations on each side (A, B, C, D) corresponds to the desired pinout of the package that the die will be assembled into, or to signal terminals on a multi-chip module (MCM) substrate onto which the die will be connected. FIG. 2 is a cutaway side view of the die showing an input pad at D2 and an output pad at B2 both connected to the FCL.
FIG. 3A shows an example wafer containing 64 of the die of FIG. 1. FIG. 3B shows the position of each die on the wafer with respect to sides A, D, C, and D. The phantom die in dotted line shows how the wafer would be packed to yield more die per wafer. Notice that even when the die is tightly packed on the wafer (i.e. the phantom die locations utilized), there is still area at the periphery of the wafer where die cannot be placed. This is due to the circular shape of the wafer versus the square/rectangular shape of the die. This unusable peripheral area of the wafer can be used to place test points (pads), test circuitry, and conductors for routing test signals and power and ground to die.
FIG. 4 shows how conventional die testing is performed using a tester and pad probe assembly. The probe assembly is positioned over a selected die and lowered to make contact with the die pads. Once contact is made the tester applies power and checks for high current. If current is high a short exists on the die and test is aborted and the die is marked (usually by an ink color) as bad. If current is normal, then testing proceeds by applying test patterns to the die and receiving test response from the die. If the test fails the die is marked as bad. If the test passes the die is good and not marked, or if marked, marked with a different ink color. During testing the die current can be monitored to see if it stays within a specified range during the test. An out of range current may be marked as a high current functional failure.
Such conventional wafer testing has several disadvantages. The act of probing the die scars the metal die pads. Thus, using physical probing, it is essential that dies be tested only once, since re-probing a die to repeat a test may further damage the pads. Even a single probing of a die may cause enough pad damage to adversely affect subsequent assembly of the die in IC packages or on MCM substrates. With the extremely small target provided by a die pad, the equipment used for positioning the probe on a die pad must be designed with great care and is therefore very expensive to purchase/build and maintain and calibrate. Also the stepping of the probe to each die location on the wafer takes time due to the three dimensional motions the probe must be moved through to access and test each die on the wafer.
It is therefore desirable to test die on wafers without the disadvantages described above.
The present disclosure provides: a die framework comprising die resident circuitry and connections to selectively provide either a bypass mode wherein the die has direct pad-to-pad connectivity or a functional mode wherein the die has die pad to functional core logic connectivity; a fault tolerant circuit and method to select a die on a wafer to be placed in functional mode while other die remain in bypass mode; a method and apparatus for (1) electronically selecting one die on a wafer to be placed in functional mode for testing while other die on the wafer are in bypass mode, (2) testing that selected die, and (3) repeating the electronic selection and testing steps on other die; and a method and apparatus for (1) electronically selecting a plurality of diagonally positioned die on the wafer to be placed in functional mode for testing while other die on the wafer are in bypass mode, (2) testing the selected group of diagonally positioned die in parallel, and (3) repeating the electronic selection and testing steps on other groups of diagonally positioned die.
The present disclosure provides improved testing of unsingulated die on wafer. The disclosure provides the following exemplary improvements: (1) electronic selection and testing of unsingulated die on wafer, (2) faster testing of dies on wafer, (3) elimination of expensive, finely designed mechanical wafer probes, (4) the ability to at-speed test unsingulated die on wafer. (5) the ability to test a plurality of unsingulated die in parallel, and (6) the ability to simplify the burn-in testing of unsingulated die.